This invention relates to a code converting circuit and more particularly, a code converting circuit which converts input codes having variable length into parallel N bit data in word units.
For the purpose of improving the efficiency of data compression, various methods of forming codes with variable lengths have been used in apparatus, such as an anticipative encoding apparatus, for compressing such data signal quantities as facsimile signals and television signals to be transmitted. On the transmission side of the compressing apparatus of the type referred to above, the data converted into codes of fixed length are generally sent to a transmission path as serial codes, whereas in the decoding circuit, on the receiving side, the serial codes sent from the encoding circuit are converted into parallel codes for the purpose of increasing the decoding speed. However, since the serial codes sent from the encoding circuit consist of codes having variable length, when the serial codes are converted into parallel codes in the decoding circuit, it is difficult to determine the beginning and the end of each N bits of the fixed length codes. As a result, when such decoding is executed by hardware, the decoding apparatus is quite bulky.
Furthermore, if a device, such as a computer, to which the codes having variable lengths are to be sent, is constructed to input and output the data in terms of word units, it is necessary to rearrange the codes having variable length into parallel codes having word unit length and then send the parallel codes.